The present invention relates to an on-chip voltage regulator and, more particularly, to a System on Chip (SoC) having on-chip voltage regulation and a digital logic controller for regulating the voltage of a SoC.
Conventionally, SoCs are designed to cater for worst-case timing performance. Generally speaking, a SoC works faster during higher voltage and lower ambient temperature conditions. Lower voltage and/or higher temperature necessarily results in a slower operation of the SoC. This means that the SoC must be designed to ensure that the timing of the critical paths must be met at reduced voltage and/or increased temperature conditions to ensure adequate operation of the SoC. The SoC designer must take due consideration of the PVT (process, voltage, temperature) corners; process variations must also be considered because due to small variations during manufacturing, two chips can have slightly different characteristics, meaning that they operate at slightly different speeds when compared with one another under the same conditions for voltage and temperature.
However, during the majority of the operational time of the SoC, the SoC operates in better than the worst-case conditions in terms of the three parameters: process, voltage and temperature. Therefore, in such conditions the critical path of the SoC will have sufficient positive slack, meaning that the SoC is running in excess of its worst-case performance requirement. In such circumstances, SoC voltage is higher than necessary and the excess performance can be considered to correspond to excess consumed power. This is particularly wasteful given that the dynamic power is proportional to voltage, more precisely to the square of the voltage.
For instance, a specific application for the SoC, e.g., an automotive application, might require a worst-case operating scenario where the SoC must operate at a target frequency of 200 MHz. However, the prevailing environmental conditions are usually better, perhaps much better, than the worst-case scenario. In these circumstances, the SoC is capable of operating at a higher frequency if operating at a higher voltage and/or a lower ambient temperature or manufactured in a faster process corner. However, since the minimum guaranteed operating frequency is only 200 MHz (which must be met at all times), capacity is wasted.
Dynamic Voltage Scaling (DVS) is a voltage regulation feedback system used to control supply voltage dynamically according to performance requirements. DVS is particularly beneficial in mobile applications where electrical and electronic components are powered by a battery, across a broad range of technologies from mobile computing (including mobile communications devices) to, for example, automotive applications. By exploiting the variations associated with different computational requirements for a device such as a SoC at different times in its operational cycle, the average energy of the device can be reduced while maintaining acceptable processing capacity. It therefore follows that the battery life can be extended and/or the physical size of the battery can be reduced.
In one known system a hybrid open-loop/closed-loop voltage regulation circuit is implemented. A temperature-insensitive value of a ring oscillator is used to index a lookup table (LUT). From this, the particular state or mode of operation of the system is identified and the required target frequency is derived, also from the LUT. The target supply voltage for the system is set according to the target frequency for the identified process. Once the voltage settles at the target voltage, the voltage regulation system switches to a closed-loop configuration in which the target frequency is compared to a frequency of a critical path of the system for voltage fine tuning. That is, in the closed-loop configuration fine-tuning is effected to maintain the voltage at the level identified from the LUT.
However, this requires the implementation of LUTs, which is a significant drawback considering the effort required in the compilation of the look up tables, characterization of the electronic device across a broad range of operating conditions, and a wide range of device samples that can easily run into the millions.
Implementation of DVS techniques may be further complicated in zero-defect engineering applications, such as in the automotive industry. This is because automotive customers require close to 0 PPM failure rate. One must have close controllability of voltages and implement hard thresholds for voltage conditions that are required for correct functioning.
Thus, it would be advantageous to develop one or more new techniques that alleviate the aforementioned problems.